Semiconductor integrated circuit device and method for desiging the same

ABSTRACT

A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No.10/935,094, filed Sep. 8, 2004, which is a Divisional of U.S.application Ser. No. 10/252,563, filed Sep. 24, 2002, now U.S. Pat. No.6,791,128, claiming priority of Japanese Application No. 2001-329582,filed Oct. 26, 2001, the entire contents of each of which are herebyincorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice which matches the trend toward further miniaturization and to amethod for designing the same.

If a plurality of functional blocks are formed in one chip, it has notbeen performed conventionally to provide MOS transistors contained in aplurality of digital functional circuit blocks with different gatelengths or provide the respective gate oxide films of the MOStransistors with different thicknesses.

Briefly, in a conventional circuit designing method, on-chipmicro-patterning is regulated by one design rule and a reduction inmargin resulting from patterning variations is compensated for by usinga uniform value. The reason for a uniform margin allowed is that adifference of one order of magnitude or more exists between a requiredperformance value and a required margin. In an exemplary case, aspecification for a required access time is 3.0 ns, a mean value ofactually obtained access times is 2.5 ns, and a required marginconsidering patterning variations is 0.3 ns. In the case where thespecification for the required access time is set to 0.4 ns, however, ifthe mean value of actually obtained access times is improved to 0.25 nsand a margin of 0.30 ns is allowed, the improvement in performance issuppressed by the margin for patterning variations.

This indicates that, as increasingly higher performance is required infuture, if a uniform margin for patterning variations is providedthroughout the entire chip, an improvement in performance is suppressedby the uniform margin.

In other words, it becomes difficult to satisfy required performancethroughout the entire chip, though the required performance is satisfiedlocally in a portion of the chip. As a result, the performance of thechip is limited by the worst portion of the entire chip so that theperformance is not improved.

In an analog circuit or a circuit for which consideration should begiven to a latch-up caused by an electrostatic damage (ESD) or to abreakdown voltage, it has been a conventional practice to use differentdesign rules for a transistor provided on the I/O pad portion of thecircuit and for the logic portion of the circuit. This is becausedifferent power supply voltages are applied thereto.

Thus, it has not been performed conventionally to use different designrules in one digital circuit block or in one analog circuit. It has notbeen performed, either, to divide one wafer into chips of differentsizes or fabricate, from one wafer, various chips designed to havedifferent functions or performances on a per chip basis.

As design sizes are reduced increasingly year after year, the design ofa chip performed by applying one design rule to one chip encounters thefollowing problems.

The design rule which is 0.13 μm in the year 2001 is expected to become0.10 μM in the year 2005. If design is to be performed in accordancewith the design rule of 0.10 μm, a fabrication process requires apatterning accuracy on the order of several tens of nanometers.

In that case, it will become extremely difficult to control variationsin patterning accuracy to several tens of nanometers in consideration ofeach of variations in patterning accuracy in the fabrication processdepending on the regions of the principal surface (portion) of a wafer,the relationship between the regions (portions) of one chip and layoutdensities therein, and the like.

If design rules also considering variations in patterning accuracy areapplied, a design margin is reduced dramatically so that the yield rateis reduced significantly. As a consequence, the trend toward furtherminiaturization drastically increases the manufacturing cost for a chip.

SUMMARY OF THE INVENTION

In view of the foregoing problems expected, an object of the presentinvention is to positively match the trend toward a further reduction indesign size.

As a result of examining a performance required of each of a pluralityof functional blocks integrated in one chip, the present inventor hasconcluded that an operating speed, a leakage current, and the like neednot necessarily be the same for each of the functional blocks. In asystem LSI using a design rule of 0.10 μm or less which implementsultraminiaturization technology, in particular, all devices required forthe system LSI are integrated with each other so that the trend towardthe use of a different operating speed, a different leakage current, andthe like for each of functional blocks will probably grow.

To attain the object, the present invention provides a semiconductorintegrated circuit device which is constructed such that:

(1) if different finished sizes resulting from geometric features arepredictable for design patterns containing elements and wires formed onone chip,

(2) if finished sizes are different depending on electric specificationsrequired of the design patterns and on designing means (methods) forimplementing the electric specifications, or

(3) if required specifications are different depending on usage modes inthe design patterns,

performance variations resulting from patterning variations andvariations in required performance are complemented by each other. Itfollows therefore that circuit elements or wires in a semiconductorintegrated circuit device formed on one substrate have a plurality ofminimum sizes values.

Specifically, a first semiconductor integrated circuit device accordingto the present invention comprises: a plurality of design patternscomposed of circuit elements or wires formed on a substrate, respectivefinished sizes of the plurality of design patterns having a plurality ofminimum size values which differ from one design pattern to anotherdepending on a geometric feature of each of the design patterns.

In the first semiconductor integrated circuit device, design margins forthe plurality of design patterns are not uniform so that an improvementin the performance of the device is not suppressed by a margin forpatterning variations.

Preferably, in the first semiconductor integrated circuit device, theplurality of minimum size values are set for a length or width of eachof parts composing the circuit elements, a spacing between the parts, anoverlapping portion between the parts, or a configuration of aprotruding portion of the part and are set for a width of each of thewires or a spacing between the wires.

Preferably, in the first semiconductor integrated circuit device, thecircuit elements are bit cells in a memory device and an area occupiedby each of the bit cells is determined by any of the plurality ofminimum size values.

Preferably, in the first semiconductor integrated circuit device, thecircuit elements are contained in an element formation layer and thewires are contained in a wiring layer, the device further comprising:one or more contacts for providing an electric connection between theelement formation layer and the wiring layer, the minimum size value ofthe finished size of each of the contacts depending on an area occupiedby the contact on the substrate or on the number of the contacts.

Preferably, in the first semiconductor integrated circuit device, thegeometric feature is respective directions or positions of the circuitelements or the wires on the substrate and the plurality of minimum sizevalues are set to correct dependence of the finished sizes on thedirections or positions on the substrate.

Preferably, in the first semiconductor integrated circuit device, thegeometric feature is a layout density of the circuit elements or thewires on the substrate and the plurality of minimum size values are setto correct dependence of the finished sizes on the layout density.

Preferably, in the first semiconductor integrated circuit device, thecircuit elements are bit cells in a memory device, the geometric featureis a layout type of the bit cells, and the plurality of minimum sizevalues are set to correct dependence of the finished size on arelationship between a direction in which a gate of a drive transistorextends and a direction in which a gate of an access transistorconnected to a word line extends in each of the bit cells.

Preferably, in the first semiconductor integrated circuit device, thegeometric feature is the presence or absence of a dummy pattern which isa dummy of each of the design patterns contained therein and, if thedummy patterns are contained in the design pattern, the plurality ofminimum size values are set to correct dependence of the finished sizeon the dummy pattern.

A second semiconductor integrated circuit device according to thepresent invention comprises: a plurality of design patterns composed ofcircuit elements or wires formed on a substrate, the plurality of designpatterns having a plurality of minimum size values which differ from onedesign pattern to another depending on different finished sizesresulting from an electric specification of each of the design patternsand a designing means for implementing the electric specification.

In the second semiconductor integrated circuit device, design marginsfor the plurality of design patterns are not uniform so that animprovement in the performance of the device is not suppressed by amargin for patterning variations.

Preferably, in the second semiconductor integrated circuit device, theplurality of minimum size values are set for a length or width of eachof parts composing the circuit elements, a spacing between the parts, anoverlapping portion between the parts, or a configuration of aprotruding portion of the part and are set for a width of each of thewires or a spacing between the wires.

Preferably, in the second semiconductor integrated circuit device, thecircuit elements are bit cells in a memory device and an area occupiedby each of the bit cells is determined by any of the plurality ofminimum size values.

Preferably, in the second semiconductor integrated circuit device, thecircuit elements are contained in an element formation layer and thewires are contained in a wiring layer, the device further comprising:one or more contacts for providing an electric connection between theelement formation layer and the wiring layer, the minimum size value ofthe finished size of each of the contacts depending on an area occupiedby the contact on the substrate or on the number of the contacts.

A third semiconductor integrated circuit device according to the presentinvention comprises: a design pattern composed of a plurality of circuitelements or the wires formed on a substrate, the design pattern having aplurality of minimum size values in a spacing between parts at differentpotentials during standby which differ depending on an electricspecification and a designing means for implementing the electricspecification.

In the third semiconductor integrated circuit device, design margins forthe plurality of design patterns are not uniform so that an improvementin the performance of the device is not suppressed by a margin forpatterning variations.

Preferably, in the third semiconductor integrated circuit device, theparts at different potentials during standby are formed in differentlayers.

Preferably, in the second or third semiconductor integrated circuitdevice, the electric specification is suppression of a leakage currentand the designing means includes at least one of power voltage control,power shutdown control, threshold voltage control, and gate-to-sourcepotential control.

Preferably, in the second or third semiconductor integrated circuitdevice, the electric specification is an operating speed and thedesigning means includes at least one of power voltage control,threshold voltage control, and delay control effected by usingvariations in the number of wiring layers used in a layout.

Preferably, in the second or third semiconductor integrated circuitdevice, the electric specification is a timing value and the designingmeans includes at least one of selection of synchronous design orasynchronous design, delay control effected by using variations in thenumber of wiring layers used in a layout, a delay circuit for timingadjustment, a gate size of a transistor, and a layout for adjusting adistance from a clock driver.

Preferably, in the second or third semiconductor integrated circuitdevice, the circuit elements are memory elements and the designing meansis a means for imparting a redundancy function for saving a defect.

A fourth semiconductor integrated circuit device according to thepresent invention comprises: a plurality of design patterns composed ofcircuit elements or wires formed on a substrate, the plurality of designpatterns having a plurality of minimum size values which differ from onedesign pattern to another depending on different required specificationsdependent on usage modes thereof.

In the fourth semiconductor integrated circuit device, design marginsfor the plurality of design patterns are not uniform so that animprovement in the performance of the device is not suppressed by amargin for patterning variations.

Preferably, in the fourth semiconductor integrated circuit device, thecircuit elements are composed of a plurality of memory elements and theusage modes and the required specifications are set to tolerate a faultin some of the plurality of memory elements.

Preferably, in the fourth semiconductor integrated circuit device, thecircuit elements are memory elements and the usage modes and therequired specifications are such that the memory elements do not retaindata during standby.

A first method for designing a semiconductor integrated circuit deviceaccording to the present invention comprises the step of: forming, on asubstrate, a plurality of design patterns composed of circuit elementsor wires, wherein a plurality of design rules having different valuesare applied to the plurality of design patterns by using dependence ofrespective finished sizes of the design patterns on a geometric featureof each of the design patterns.

In accordance with the first method for designing a semiconductorintegrated circuit device, design margins for the plurality of designpatterns are not uniform so that an improvement in the performance ofthe device is not suppressed by a margin for patterning variations.

Preferably, in the first method for designing a semiconductor integratedcircuit device, the plurality of design rules are applied to a length orwidth of each of parts composing the circuit elements, a spacing betweenthe parts, an overlapping portion between the parts, or a configurationof a protruding portion of the part and are applied to a width of eachof the wires or a spacing between the wires.

Preferably, in the first method for designing a semiconductor integratedcircuit device, the circuit elements are bit cells in a memory deviceand an area occupied by each of the bit cells is determined by any ofthe plurality of design rules.

Preferably, the first method for designing a semiconductor integratedcircuit device further comprises the step of forming one or morecontacts for providing electric connections between the circuit elementsand the wires, wherein any of the plurality of design rules is appliedby using dependence of the finished size of each of the contacts on anarea occupied by the contact on the substrate or on the number of thecontacts.

Preferably, in the first method for designing a semiconductor integratedcircuit device, the geometric feature is directions or positions of thecircuit elements or the wires on the substrate and the plurality ofdesign rules are set to correct dependence of the finished sizes on thedirections or positions on the substrate.

Preferably, in the first method for designing a semiconductor integratedcircuit device, the geometric feature is a layout density of the circuitelements or the wires on the substrate and the design rules are set tocorrect dependence of the finished sizes on the layout density.

Preferably, in the first method for designing a semiconductor integratedcircuit device, the circuit elements are bit cells in a memory device,the geometric features is a layout type of the bit cells, and theplurality of design rules are set to correct dependence of the finishedsize on a relationship between a direction in which a gate of a drivetransistor extends and a direction in which a gate of an accesstransistor connected to a word line extends in each of the bit cells.

Preferably, in the first method for designing a semiconductor integratedcircuit device, the geometric feature is the presence or absence of adummy pattern which is a dummy of each of the design patterns containedtherein and, if the dummy patterns are contained in the design pattern,the design rules are set to correct dependence of the finished size onthe dummy pattern.

A second method for designing a semiconductor integrated circuit deviceaccording to the present invention comprises the step of forming, on asubstrate, a plurality of design patterns composed of circuit elementsor wires, wherein a plurality of design rules having different valuesare applied to the plurality of design patterns depending on differentfinished sizes resulting from an electric specification of each of thedesign patterns and a designing method for implementing the electricspecification.

In accordance with the second method for designing a semiconductorintegrated circuit device, design margins for the plurality of designpatterns are not uniform so that an improvement in the performance ofthe device is not suppressed by a margin for patterning variations.

Preferably, in the second method for designing a semiconductorintegrated circuit device, the plurality of design rules are applied toa length or width of each of parts composing the circuit elements, aspacing between the parts, an overlapping portion between the parts, ora configuration of a protruding portion of the part and are applied to awidth of each of the wires or a spacing between the wires.

Preferably, in the second method for designing a semiconductorintegrated circuit device, the circuit elements are bit cells in amemory device and an area occupied by each of the bit cells isdetermined by any of the plurality of design rules.

Preferably, the second method for designing a semiconductor integratedcircuit device further comprises the step of forming one or morecontacts for providing electric connections between the circuit elementsand the wires, wherein any of the plurality of design rules is appliedby using dependence of the finished size of each of the contacts on anarea occupied by the contact on the substrate or on the number of thecontacts.

A third method for designing a semiconductor integrated circuit deviceaccording to the present invention comprises the step of: forming, on asubstrate, a plurality of design patterns composed of circuit elementsor wires, wherein the plurality of design patterns include a spacingbetween parts at different potentials during standby and a plurality ofdesign rules are applied to the plurality of design patterns dependingon an electric specification of each of the design patterns and adesigning method for implementing the electric specification.

In accordance with the third method for designing a semiconductorintegrated circuit device, design margins for the plurality of designpatterns are not uniform so that an improvement in the performance ofthe device is not suppressed by a margin for patterning variations.

Preferably, in the third method for designing a semiconductor integratedcircuit device, the parts at different potentials during standby areformed in different layers.

Preferably, in the second or third method for designing a semiconductorintegrated circuit device, the electric specification is suppression ofa leakage current and the designing method includes at least one ofpower voltage control, power shutdown control, threshold voltagecontrol, and gate-to-source potential control.

Preferably, in the second or third method for designing a semiconductorintegrated circuit device, the electric specification is an operatingspeed and the designing method includes at least one of power voltagecontrol, threshold voltage control, and delay control effected by usingvariations in the number of wiring layers used in a layout.

Preferably, in the second or third method for designing a semiconductorintegrated circuit device, the electric specification is a timing valueand the designing method includes at least one of selection ofsynchronous design or asynchronous design, delay control effected byusing variations in the number of wiring layers used in a layout, adelay circuit for timing adjustment, a gate size of a transistor, and alayout for adjusting a distance from a clock driver.

Preferably, in the second or third method for designing a semiconductorintegrated circuit device, the circuit elements are memory elements andthe designing method is a method for imparting a redundancy function forsaving a defect.

A fourth method for designing a semiconductor integrated circuit deviceaccording to the present invention comprises the step of: forming, on asubstrate, a plurality of design patterns composed of circuit elementsor wires, wherein a plurality of design rules having different valuesare applied to the plurality of design patterns depending on differentrequired specifications dependent on respective usage modes of thedesign patterns.

In accordance with the fourth method for designing a semiconductorintegrated circuit device, design margins for the plurality of designpatterns are not uniform so that an improvement in the performance ofthe device is not suppressed by a margin for patterning variations.

Preferably, in the fourth method for designing a semiconductorintegrated circuit device, the circuit elements are composed of aplurality of memory elements and the usage modes and the requiredspecifications are set to tolerate a fault in some of the plurality ofmemory elements.

Preferably, in the fourth method for designing a semiconductorintegrated circuit device, the circuit elements are memory elements andthe usage modes and the required specifications are set such that thememory elements do not retain data during standby.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a category system of physical dimensions (physicaldimensions to be applied) to be applied to design patterns composing asemiconductor integrated circuit device according to the presentinvention;

FIG. 2 shows a category system of geometric features in the designpatterns composing the semiconductor integrated circuit device accordingto the present invention;

FIG. 3A is a plan view diagrammatically showing a chip-likesemiconductor integrated circuit device according to a first embodimentof the present invention and SRAM blocks formed on the chip;

FIG. 3B is a table of physical dimensions and conditions to be appliedto the SRAM blocks of FIG. 3A;

FIG. 4 is a plan view diagrammatically showing the chip shown in FIG. 3Awhich is formed on a wafer and bit cells contained in the SRAM blocksformed on the chip;

FIG. 5 is a plan view diagrammatically showing a. chip-likesemiconductor integrated circuit device according to a second embodimentof the present invention;

FIG. 6 is a plan view diagrammatically showing a chip-like semiconductorintegrated circuit device according to a third embodiment of the presentinvention;

FIG. 7 is a plan view diagrammatically showing a chip-like semiconductorintegrated circuit device according to a fifth embodiment of the presentinvention which is formed on a wafer and bit cells contained in SRAMblocks formed on the chip;

FIG. 8 is a plan view showing a plurality of bit cells contained in anSRAM block formed in a semiconductor integrated circuit device accordingto a sixth embodiment of the present invention;

FIG. 9 is a plan view showing a plurality of bit cells contained in anSRAM block formed in a semiconductor integrated circuit device accordingto the sixth embodiment;

FIG. 10 shows a category system of electric specifications in the designpatterns composing the semiconductor integrated circuit device accordingto the present invention and designing means for implementing theelectric specifications;

FIGS. 11A and 11B show an SRAM block formed in a semiconductorintegrated circuit device according to a seventh embodiment of thepresent invention, of which FIG. 11A is a partial circuit diagramshowing an SRAM block in which current voltage control is performed andFIG. 11B is a plan view showing bit cells contained in the SRAM block;

FIGS. 12A and 12B show another SRAM block formed in the semiconductorintegrated circuit device according to the seventh embodiment, of whichFIG. 12A is a partial circuit diagram showing the SRAM block in whichcurrent voltage control is not performed and FIG. 11B is a plan viewshowing bit cells contained in the SRAM block;

FIGS. 13A to 13C show an SRAM block formed in a semiconductor integratedcircuit device according to an eighth embodiment of the presentinvention, of which FIG. 13A is a partial circuit diagram showing theSRAM block in which power shutdown control is performed and FIGS. 13Band 13C are cross-sectional views showing bit lines and ground lines inthe SRAM block;

FIGS. 14A and 14B show an SRAM block formed in a semiconductorintegrated circuit device according to a ninth embodiment of the presentinvention, of which FIG. 14A is a partial circuit diagram showing theSRAM block in which power shutdown control is not controlled and FIG.14B is a cross-sectional view showing bit lines and ground lines in theSRAM blocks;

FIG. 15A is a table of physical dimensions and conditions to be appliedto design patterns in SRAM blocks formed on a chip-like semiconductorintegrated circuit device according to a twelfth embodiment of thepresent invention;

FIG. 15B is a plan view diagrammatically showing SRAM blocks satisfyingthe conditions shown in FIG. 15A;

FIGS. 16A and 16B show the respective structures of SRAM blocksaccording to the twelfth embodiment, of which FIG. 16A is a blockdiagram of the SRAM circuit having a redundancy function and FIG. 16B isa block diagram of the SRAM circuit not having a redundancy function;

FIG. 17 is a graph showing the relationship between the DD value of alogic portion and the DD value of an SRAM portion in the SRAM blocksaccording to the twelfth embodiment at each time of inspection;

FIG. 18A is a plan view when two contacts are provided in a specifiedregion;

FIG. 18B is a plan view when one contact is provided in a specifiedregion;

FIG. 19 shows a category system of usage modes in the design patternscomposing the semiconductor integrated circuit device according to thepresent invention;

FIG. 20A is a table of physical dimensions and conditions to be appliedto design patterns in SRAM blocks formed on a chip-like semiconductorintegrated circuit device according to a thirteenth embodiment of thepresent invention;

FIG. 20B is a plan view diagrammatically showing SRAM blocks satisfyingthe conditions shown in FIG. 20A;

FIGS. 21A and 21B show an SRAM block formed in a semiconductorintegrated circuit device according to a fourteenth embodiment of thepresent invention, of which FIG. 21A is a partial circuit diagramshowing the SRAM block in which power shutdown control is performed andFIG. 21B is a cross-sectional view showing bit lines and ground lines inthe SRAM block; and

FIGS. 22A and 22B show an SRAM block formed in a semiconductorintegrated circuit device according to the fourteenth embodiment, ofwhich FIG. 22A is a partial circuit diagram showing the SRAM block inwhich power shutdown control is not performed and FIG. 22B is across-sectional view showing bit lines and ground lines in the SRAMblock.

DETAILED DESCRIPTION OF THE INVENTION

A description will be given first to “the case where different finishedsizes resulting from geometric features are predictable”, which is afirst concept of the present invention.

A semiconductor integrated circuit device based on the first concept ofthe present invention comprises design patterns composed of a pluralityof circuit elements or wires formed on a semiconductor substrate. Therespective finished sizes of the design patterns have a plurality ofminimum size values which differ from one design pattern to anotherdepending on the geometric feature of each of the design patterns.

In other words, if the plurality of circuit elements composing thesemiconductor integrated circuit device are assumedly contained in oneelement formation layer and the plurality of wires are contained in onewiring layer, a plurality of design rules having different values on aper layer basis are applied to the respective design patterns in theelement formation layer and in the wiring layer depending on thedifferent finished sizes resulting from the geometric features on thesubstrate.

A description will be given herein below to the categories of the designrules according to the present invention.

As shown in FIG. 1, the design rules for determining physical dimensions(physical dimensions to be applied) to be applied to the design patternsare grouped into, e.g., the following five categories.

The first category is relative design-rule sizes in a layout designprocess. The relative design-rule sizes are a set of design patternsdirectly proportional to the square of an F value representing aninverse number of an aperture ratio. For example, the relativerule-sizes of the circuit elements include the lengths and widths of theparts of the circuit elements, the space (spacing) between the parts, anoverlap (overlapping portion) between the parts, and the configurationsof the protruding portions of the parts. The relative design-rule sizesof the wires are the widths of the wires or the space between the wires.

If the circuit elements are assumed to be field-effect transistors(FETs), the lengths or widths of the parts can be subdivided into gatelengths, gate widths, and the widths of active regions (n⁺OD, p⁺OD). Thewidth of an active region (OD: Oxide Definition) in a FET indicates awidth in the gate width direction in source/drain regions.

The space between the parts can be subdivided into a gate-to-gatespacing, a gate-to-contact spacing, a wire-to-contact spacing, a spacingbetween an n-type well (NW) and an n-type active region, and a spacingbetween a p-type well (PW) and a p-type active region.

The protrusions include, e.g., the size of a protruding portion from thegate.

The design-rule values used herein are not necessarily the sizes of amask and indicate actual finished sizes (expected values) after processpatterning.

The second category is the thicknesses of the parts in the designpatterns, which are, e.g., the respective thicknesses of gate insulatingfilms, gates, insulating films, and wire films in FETs.

The third category is, if the design pattern is for, e.g., cells (bitcells) each composing one bit in a memory (storage) circuit, an areaallowed for each of the bit cells in laying out the bit cells in thelayout design process, i.e., a bit cell area.

The fourth category is areas occupied by the design patterns on thesubstrate. If contacts providing electric connections between thecircuit elements contained in the element formation layer and the wirescontained in the wiring layer are taken as an example, the fourthcategory is the layout area of the contacts or the number of thecontacts occupying the layout area. Otherwise, the fourth category isareas occupied by n-type wells and p-type wells or areas occupied by thegates of FETs.

The fifth category is a layout of nodes at different potentials(different-potential nodes), which is the determination of whether thedifferent-potential nodes are laid out in one layer or in differentlayers.

The physical dimensions used herein include sizes to be appliedintentionally or inevitably.

A description will be given next to conditions for determining whetheror not these design rules are to be applied to the design patterns.

FIG. 2 shows the geometric features of the design patterns which aredivided into five groups. As shown in FIG. 2, the first geometricfeature is the directions or positions (regions) of the design patternson the substrate. The plurality of minimum size values of the designpatterns according to the first embodiment are set to correct thedependence of the finished sizes on the directions or positions(regions) of the design patterns on the substrate.

EMBODIMENT 1

A first embodiment of the present invention will be described hereinbelow with reference to the drawings.

FIG. 3A diagrammatically shows a plan structure of a chip-likesemiconductor integrated circuit device according to the firstembodiment and static random access memory (SRAM) blocks formed on thechip.

As shown in FIG. 3A, a first SRAM block 11 having a capacity of 512kbits, a second SRAM block 12 having a capacity of 128 kbits, and athird SRAM block having a capacity of 16 kbits are formed integrally ona principal surface of a chip 10 composed of, e.g., silicon.

Here, an area (S_bitcell) occupied by a cell corresponding to one bit(bit cell) which composes the first SRAM block 11 is assumed to be 2.4μm² and an area occupied by a cell corresponding to one bit (bit cell)which composes the second and third SRAM blocks 12 and 13 is assumed tobe 3.5 μm².

As shown in FIG. 3B, the physical dimension to be applied shown in FIG.1 is assumed to be “Bit Cell Area” and the condition to be applied shownin FIG. 2 is assumed to be “Direction”, which is the first geometricfeature.

As a result, the directions (gate width directions) in which the gatesof the plurality of transistors composing the bit cells extend are setto specified directions in which conditions for lithography areoptimized.

Thus, in the SRAM device according to the first embodiment, the bit cellarea has been set to have different values depending on the gate widthdirections of the transistors composing the bit cells.

A detailed description will be given to the specified directions on thechip 10 with reference to the drawings.

FIG. 4 diagrammatically shows each of the plurality of chips 10 which isformed on a wafer 1. As shown in FIG. 4, a bit cell 11 a contained inthe first SRAM block 11 has six transistors MN0, MN1, MN2, MN3, MP0, andMP1.

As has been well known, the first n-type drive transistor MN0 and thefirst p-type load transistor MP0 constitute a first CMOS inverter, whilethe second n-type drive transistor MN1 and the second p-type loadtransistor MP1 constitute a second CMOS inverter. Each of the first andsecond inverts has an input node connected in cross-coupled relation tothe output node of the other.

The first access transistor MN2 is connected to the output node of thefirst CMOS inverter, while the second access transistor MN3 is connectedto the output node of the second CMOS inverter.

The first N-type drive transistor MN0 and the first P-type loadtransistor MP0 share a first gate 21, while the second N-type drivetransistor MN1 and the second P-type load transistor MP1 share a secondgate 22.

The third gate 23 of the first access transistor MN2 having a drainshared by the first N-type drive transistor MN0 and the first P-typeload transistor MP2 is provided in parallel with the first and secondgates 21 and 22.

Likewise, the fourth gate 24 of the second access transistor MN3 havinga drain shared by the second N-type drive transistor MN1 and the secondP-type load transistor MP1 is also provided in parallel with the firstand second gates 21 and 22.

Thus, the respective gates 21 to 24 of the six transistors MN0, MN1,MN2, MN3, MP0, and MP1 have their gate width directions coincident withthe direction of the X axis which is parallel with, e.g., theorientation flat (OF) of the wafer 1.

On the other hand, a bit cell 12 a contained in the second SRAM block 12has the same structure as the bit cell 11 a, as shown in FIG. 4. In thedrawings, like parts are designated by like reference numerals. Each ofthe first to fourth gates 21 to 24 composing the bit cell 12 a has itsgate width direction oriented in the direction of the Y axis.Consequently, the gate width directions of the first to fourth gates 21to 24 composing the bit cell 12 a are orthogonal to the gate widthdirections of the first to fourth gates 21 to 24 composing the bit cell11 a.

This optimizes the conditions for lithography performed with respect tothe first SRAM block 11 having the gates extending in the direction ofthe X axis and reduces gate-related dimensions, e.g., a gate length, agate-to-gate spacing, a gate-to-contact spacing, and the like, comparedwith those of the transistors contained in the second SRAM block 12. Asa result, the area occupied by the bit cell in the first SRAM block 11can be reduced to 2.4 μm, which is smaller than the area occupied by thebit cell in the second SRAM block 12.

In the second SRAM block 12, on the other hand, the longitudinaldirections of the parts in the design patterns coincide with thedirection of the Y axis. Accordingly, the dimensions including the gatelength and the gate-to-contact spacing should be increased. As a result,the area occupied by the bit cell in the second SRAM block 12 isincreased to 3.5 μm, which is larger than the area occupied by the bitcell in the first SRAM block 11.

In performing, e.g., patterning for determining the respective gatelengths of the gates 21 to 24 in the first and second SRAM blocks 11 and12, it is generally difficult to suppress patterning variations in alithographic step and in an etching step in all directions, i.e.,without specifying the direction to the direction of the X axis or the Yaxis.

Since the first embodiment can retain required patterning accuracy byspecifying the directions (gate width directions) in which the gatesextend to the direction of the X axis in at least one of the pluralityof functional blocks and preferentially optimizing the conditions forlithography in the specified direction, it can achieve an access time, alow leakage current, or the like required for the bit cell 11 a.

In this case, the conditions for lithography in another directiondeviated from the specified direction, e.g., in the direction of the Yaxis have not been optimized. Therefore, patterning accuracy, i.e., themaximum size value of the design pattern should be sacrificed. For thebit cell 12 a which is laid out to have the gate width directionsoriented in a direction involving the sacrifice, i.e., only in thedirection of the Y axis, the dimensions including the gate lengths andthe gate-to-contact spacings are increased even at the expense of areduction in the area occupied by the bit cell 12 a such that thecircuit elements are machined exactly as designed.

As shown in FIG. 3, the first SRAM block 11 has a large memory capacityand occupies a large area on the chip 10, while the second SRAM block 12has a small memory capacity and occupies an area smaller than thatoccupied by the first SRAM block 11 on the chip 10. In the first SRAMblock 11, therefore, the conditions for lithography and etching areoptimized by giving a higher priority to gate width directions so thatthe maximum size value which reduces the bit cell area is appliedthereto. To the second SRAM block 12 which should be sacrificed in termsof process conditions, on the other hand, the minimum size value largerthan the minimum size value applied to the first SRAM block 11 isapplied.

Thus, according to the first embodiment, the layout of the first SRAMblock 11 which has a large capacity and in which the bit cell area is tobe further reduced is limited to a specified direction. To the secondSRAM block 12 free from the limitation and having a smaller memorycapacity, a relatively large bit cell area is applied. This reduces thearea of each of the first and second SRAM blocks 11 and 12 so that thearea of the chip 10 is reduced resultantly.

Although the first embodiment has described the SRAM blocks formed inthe semiconductor integrated circuit device, the functional blocks arenot limited to the SRAM blocks.

EMBODIMENT 2

A second embodiment of the present invention will be described hereinbelow with reference to the drawings.

FIG. 5 diagrammatically shows a plan structure of a chip-likesemiconductor integrated circuit device according to the secondembodiment.

In the second embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Relative Design-Rule Sizes” and the conditionto be applied shown in FIG. 2 is assumed to be “Position or Region”.

As shown in FIG. 5, the principal surface of the chip 10 is partitionedinto first, second, third, and fourth regions 31, 32, 33, and 34 atevery given radial distance from the center of the chip 10. Based on thesizes of the elements and the spacing between the individual parts ofthe elements to be applied to the first region 31 positioned at thecentral portion of the chip 10, e.g., the sizes of the elements or theparts thereof contained in the second to fourth regions 32 to 34 areincreased gradually outwardly.

For example, the F value and the bit cell area in the first region 31are assumed to be 1.0 and 2.4 μm², respectively. Since the relativedesign-rule sizes shown in FIG. 1 are directly proportional to thesquare of the F value, if the F value in the second region 32 is assumedto be 1.1, the bit cell area therein becomes 2.9 μm². If the F value inthe third region 33 is assumed to be 1.2, the bit cell area thereinbecomes 3.46 μm². If the F value in the fourth region 34 is assumed tobe 1.3, the bit cell area therein becomes 4.06 μm².

Thus, the second embodiment has optimized the conditions for lithographyor etching by setting priorities in accordance with the distances fromthe center of the chip 10. Conversely, if the conditions for lithographyor the like are optimized in accordance with the distances from theouter region of the chip 10, i.e., from the fourth region 34 toward thefirst region 31, the F value in the first region 31 becomes highestamong the F values in the first to fourth regions 31 to 34.

In another example, the gate length L in the first region 31 is assumedto be 0.15 μm and the operating frequency of an SRAM circuit therein isassumed to be 160 MHz. In the second region 32, the gate length L andthe operating frequency of the SRAM circuit are assumed to be 0.18 μmand 80 MHz, respectively. In the third region 33, the gate length L andthe operating frequency of the SRAM circuit are assumed to be 0.20 μmand 40 MHz, respectively.

As stated previously, only one process condition has been appliedconventionally throughout one chip (wafer) so that the process conditionis determined by the minimum condition in the chip 10. As a result, onetype of bit cells each having a minimum size value have been formedconventionally on one chip.

By contrast, the present invention allows size variations on the chip 10during micro-patterning to be complemented at a design stage by physicaldimensions to be applied which are capable of suppressing the variationsso that the area of the chip is reduced.

Although the second embodiment has used the SRAM device as thesemiconductor integrated circuit device, the present invention is notlimited to an SRAM device.

EMBODIMENT 3

A third embodiment of the present invention will be described hereinbelow with 10 reference to the drawings.

FIG. 6 diagrammatically shows a plan structure of a chip-likesemiconductor integrated circuit device according to the thirdembodiment. In the third embodiment also, the physical dimension to beapplied shown in FIG. 1 is assumed to be “Relative Design-Rule Sizes”and the condition to be applied is assumed to be “Position or Region”,which is the first geometric feature, in the same manner as in thesecond embodiment.

As shown in FIG. 6, a plurality of first functional blocks 15 aredisposed at the central portion of the principal surface of the chip 10and a plurality of second functional blocks 16 each occupying an areasmaller than the area occupied by each of the first functional blocks 15are disposed around the plurality of first functional blocks 15.

The following is the relationship between the respective sizes of thefunctional blocks 15 and 16 and a margin for allowable micro-patterningvariations.

(1) If the size of a block is large, as that of the first functionalblock 15, an absolute amount of variation in wiring resistance or wiringcapacitance is large so that an operating margin for micro-patterningvariations is small.

(2) If the size of a block is small, as that of the second functionalblock 16, an absolute amount of variation in wiring resistance or wiringcapacitance is small so that an operating margin for micro-patterningvariations is large.

If the distance from the center of the chip 10 is dependent on themagnitude of micro-patterning variation, the second functional blocks 16smaller in size are disposed preferentially on the peripheral region ofthe chip 10 where variations are large. On the other hand, the firstfunctional block 15 larger in size are disposed preferentially on thecentral region of the chip 10 where variations are small.

By way of example, the F value in each of the first and secondfunctional blocks 15 and 16 is assumed to be 1.0, while the respectiveareas occupied by the first block 15 and the second block 16 are assumedto be 15 mm² and 3 mm².

EMBODIMENT 4

A fourth embodiment of the present invention will be described hereinbelow with reference to the drawings.

In the fourth embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Relative Design-Rule Size” and the condition tobe applied shown in FIG. 2 is assumed to be “Layout Density”, which is asecond geometric feature.

The second geometric feature is the layout density of the circuitelements or wires on the substrate. Since the minimum size values of thedesign patterns according to the fourth embodiment have been set tocorrect the dependence of the finished sizes on the layout density, theminimum size values are not uniform with respect to the plurality ofdesign patterns so that a plurality of minimum size values exist.

The layout density used herein relates to whether or not an isolatedpattern exists in the design pattern. The layout density is judged to behigh if consecutive patterns, not an isolated pattern, of wires, thegates of transistors, contacts, and the like exist. If consecutivepatterns do not exist and only an isolated pattern exists, the layoutdensity is judged to be low.

An example of a functional block relatively high in layout density is amemory device such as an SRAM device. Not only the memory cell arrayportion of the memory device which is composed of a plurality of memorycells arranged as a matrix but also the peripheral circuit portionthereof have high layout densities. Conditions for lithography andetching are optimized more easily in the region at a high layout densitythan in a region at a low layout density. This allows design sizes to bereduced.

EMBODIMENT 5

A fifth embodiment of the present invention will be described hereinbelow with reference to the drawings.

FIG. 7 shows a plan structure of a chip-like semiconductor integratedcircuit device according to the fifth embodiment and bit cells containedin SRAM blocks formed on the chip. In FIG. 7, the description of thesame parts as shown in FIG. 4 will be omitted by retaining the samereference numerals.

In the fifth embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Bit Cell Area” and the condition to be appliedshown in FIG. 2 is assumed to be “Layout of Bit Cells”.

The third geometric feature is the layout type of bit cells in a memorydevice. Since the minimum size values according to the fifth embodimentare set to correct the dependence of the finished sizes on therelationship between the gate width directions and the direction inwhich word lines extend in the bit cells, the minimum sizes are notuniform with respect to the plurality of design patterns so that aplurality of minimum sizes exist.

As shown in FIG. 7, in a bit cell 11 a contained in a first SRAM block11 formed on the chip 10, the gate width direction of each of first tofourth gates 21 to 24 is oriented in the direction of the X axis. Here,a bit cell having a structure in which all gates are arranged inparallel with the word lines (not shown), such as the bit cell 11 a, istermed a horizontally elongated bit cell.

On the other hand, in a bit cell 12 b contained in a second SRAM block12 according to the fifth embodiment, a third gate 23 shared by firstand second access transistors MN2 and MN3 is substantially a word line,which is oriented in a direction orthogonal to a first gate 21 shared bya first N-type drive transistor MN0 and a first P-type drive transistorMP0 and to a second gate 22 shared by a second N-type drive transistorMN1 and a second P-type drive transistor MP1.

Here, a bit cell having a structure in which the first and second gates21 and 22 are arranged to cross the third gate 23 (word line), such asthe bit cell 12 b, is termed a vertically elongated bit cell.

Thus, in optimizing conditions for lithography and etching performedwith respect to the chip 10 (wafer 1), if the direction of a gate havinga higher priority is allowed to coincide with the gate width directionof the vertically elongated bit cell 11 a, a design rule which providesthe minimum one of the plurality of minimum size values in the chip 10can be applied to the bit cell 11 a, as shown in the first embodiment,so that the bit cell area is reduced to 2.4 μm².

However, since the gate width directions of the first to third gates 21to 23 are not the same in the horizontally elongated bit cell 12 b,process conditions cannot be optimized for all of the gates 21 to 23composing the bit cell 12 b. Accordingly, it is necessary to apply adesign rule larger than that applied to the first SRAM block 11, whichis a bit cell area of 3.5 μm².

Although the fifth embodiment has described the SRAM blocks formed inthe semiconductor integrated circuit device, the present invention isnot limited to SRAM blocks.

EMBODIMENT 6

A sixth embodiment of the present invention will be described hereinbelow with reference to the drawings.

FIGS. 8 and 9 show a plan structure of a plurality of bit cellscontained in SRAM blocks formed in a semiconductor integrated circuitdevice according to the sixth embodiment. In FIGS. 8 and 9, thedescription of the same parts as shown in FIG. 7 will be omitted byretaining the same reference numerals.

In the sixth embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Bit Cell Area” and the condition to be appliedshown in FIG. 2 is assumed to be “Dummy Pattern”, which is a fourthgeometric feature.

The fourth geometric feature is a dummy pattern contained in the designpattern. The minimum size value is dependent on whether or not the dummypattern is contained. If the dummy pattern is contained, the minimumsize value is set to correct the dependence of the finished size on thedummy pattern. Accordingly, the minimum size values are not uniform withrespect to the plurality of design patterns so that a plurality ofminimum size values exist.

As shown in FIG. 8, a dummy gate 40 is disposed between adjacent firstand second bit cells 41A and 41B in parallel with each of first andsecond gates 21 and 22.

Each of first and second P-type load transistors MP0 and MP1 composingthe first and second bit cells 41A and 41B has a gate length of 0.15 μm.

By contrast, the dummy gate 40 is not disposed between third and fourthbit cells 42A and 42B adjacent to each other, as shown in FIG. 9. Eachof first and second P-type load transistors MP0 and MP1 composing thethird and fourth bit cells 42A and 42B has a gate length of 0.18 μm.

To increase an access speed in an SRAM device, it is generally requiredto reduce the gate lengths of transistors composing the SRAM device. Toreduce the gate lengths, high-precision micro-patterning becomesnecessary. Since the conditions for lithography and etching areoptimized more easily in a region at a high layout density than in aregion at a low layout density, as described in the fourth embodiment,the layout densities of the first and second bit cells 41A and 41B canbe increased by disposing a dummy pattern, e.g., the dummy gate 40 in aregion where no design pattern exists.

If the dummy gate 40 is to be inserted in each of specified regions,however, automation should be provided and the layout area of dummypatterns is increased disadvantageously. In the bit cells of an SRAMdevice that have been laid out manually, not automatically, inconsideration of symmetry, the dummy gates 40 should also be disposedmanually.

In the sixth embodiment, therefore, the dummy gates 40 are disposed onlyin the SRAM blocks of which higher-speed operation is required through areduction in gate length, as in the first and second bit cells 41A and41B shown in FIG. 8. In SRAM blocks of which higher-speed operation isnot required as shown in FIG. 9, on the other hand, the gate length isincreased instead of providing the dummy gates 40.

If the gate width directions of the first and second bit cells 41A and41B provided with the dummy gates 40 are oriented in a direction whichoptimizes process conditions, as in the first embodiment, only the SRAMblocks which should be miniaturized can further be miniaturized.

Although the sixth embodiment has described the SRAM blocks formed inthe semiconductor integrated circuit device, the present invention isnot limited to SRAM blocks.

EMBODIMENT 7

A seventh embodiment of the present invention will be described hereinbelow with reference to the drawings.

A description will be given to “the case where finished sizes aredifferent depending on electric specifications required of the designpatterns and on designing means (methods) for implementing the electricspecifications”, which is a second concept of the present invention.

Specifically, in the following seventh to twelfth embodiments, thedescription will be given to the case where, if the design patterns aredependent on the electric specifications and on the designing means(methods) for implementing the electric specifications, a plurality ofdesign rules are applied to each of the first, third, fourth, and fifthdesign rules shown in FIG. 1.

FIG. 10 shows the characteristics of the electric specifications in thedesign patterns and the designing means for implementing the electricspecifications. As shown in FIG. 10, the characteristic of the firstelectric specification is “Leakage Current” in the design patterns.Examples of the designing means capable of suppressing “Leakage Current”are power voltage control, power shutdown control, threshold voltagecontrol (substrate potential control or source potential control), andgate-to-source potential difference control.

Specific examples will be described herein below.

FIGS. 11A and 11B show an SRAM block formed in a semiconductorintegrated circuit device according to an eleventh embodiment of thepresent invention, of which FIG. 11A shows a circuit structure of theSRAM block in which current voltage control is performed and FIG. 11Bshows a plan structure of bit cells contained in the SRAM block.

FIGS. 12A and 12B show another SRAM block formed in the semiconductorintegrated circuit device shown in FIG. 11A, of which FIG. 12A shows acircuit structure of the SRAM block in which current voltage control isnot performed and FIG. 12B shows a plan configuration of bit cellscontained in the SRAM block. As shown in FIGS. 11B and 12B, thestructures of the bit cells 50A and 50B are the same as the structureof, e.g., the bit cell 12 b shown in FIG. 7. In the drawings, like partsare designated by like reference numerals.

In the seventh embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Length/Width” of “Relative design-rule sizes”and the condition to be applied shown in FIG. 10 is assumed to be“Leakage Current”, which is the first electric specification.

In a typical SRAM device, a bit line BLn and a complementary bit line/BLn connected to the respective sources of first and second accesstransistors MN2 and MN3 are precharged to a power supply voltage Vcc sothat, if a line adjacent to the bit line BLn or to the complementary bitline /BLn is a line having a potential different from a potential on thebit line BLn or the complementary bit line /BLn, e.g., a ground line towhich a ground voltage Vss is applied, a defect at a design stage orduring fabrication may cause a short circuit between the adjacent lines.This causes the problem that a leakage current flows between the bitline BLn or the complementary bit line /BLn and the ground line.

To prevent the problem, in a bit cell 50A shown in FIG. 11A, a leakagesuppressing circuit 54 composed of a current control switch 52 and aresistor 53 connected in parallel is provided between a power supply forsupplying a power supply voltage Vcc to the common source of first andsecond P-type transistors MP0 and MP1 and a power supply line 51.

During standby, the power supply line 51 is disconnected from the powersupply by turning OFF the current control switch 52 so that a leakagecurrent is allowed to flow in the resistor 53. Accordingly, a voltagedrop changes an amount of voltage drop depending on the leakage currentand the voltage applied to the bit cell 50A lowers automatically so thatthe leakage current in the bit cell 50A is suppressed.

In accordance with such an electric specification, the bit cell 50Acapable of suppressing a leakage current with the leakage suppressingcircuit 54 provided therein can suppress an increase in leakage currentduring standby even if a leakage current is made more likely to flow inthe bit cell 50A by applying a design rule which reduces the respectivegate lengths Lg of gates 21, 22, and 23 composing the bit cell 50A inorder to achieve higher-speed operation of the transistors, as shown inFIG. 11A.

To an SRAM block not provided with the leakage suppressing circuit 54,on the other hand, a design rule which makes the area occupied by thebit cell 50B larger than the area occupied by the bit cell 50A byincreasing the respective gate lengths Lg of gates 21, 22, and 23 isapplied, as shown in FIG. 12A.

Although the seventh embodiment has described the SRAM block formed inthe semiconductor integrated circuit device, the present invention isnot limited to an SRAM block.

EMBODIMENT 8

An eighth embodiment of the present invention will be described hereinbelow with reference to the drawings.

In the eighth embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Space” of “Relative Design-Rule Sizes” and thecondition to be applied shown in FIG. 10 is assumed to be “LeakageCurrent”, which is the first electric specification.

FIGS. 13A to 13C show an SRAM block formed in a semiconductor integratedcircuit device, of which FIG. 13A shows a circuit structure of the SRAMblock in which power shutdown control is performed and FIGS. 13B and 13Cshow cross-sectional structures of bit lines and ground lines in theSRAM block.

As shown in FIG. 13A, the structure of a bit cell 50 is the same as thatof, e.g., the bit cell 12 b shown in FIG. 7. In the drawings, like partsare designated by like reference numerals.

The specification for the bit cell 50 shown in FIG. 13A is such thatdata need not be retained during standby. Accordingly, a power shutdownswitch 55 is provided between a power supply for supplying a powersupply voltage Vcc to the common source of first and second P-type loadtransistors MP0 and MP1 and a power supply line 51. The power shutdownswitch 55 is turned OFF during standby so as not to supply the powersupply voltage Vcc to the power supply line 51. On the other hand, thepower shutdown switch 55 is turned ON during operation so as to supplythe power supply voltage Vcc to the power supply line 51.

In the eighth embodiment also, a plurality of design rules are appliedto wiring patterns containing bit lines BLn and /BLn composing the SRAMblocks depending on electric specifications and means (methods) forimplementing the electric specifications.

In an SRAM block in which the occurrence of a leakage current duringstandby is allowed, e.g., the spacings between the bit lines BLn and/BLn formed in one wiring layer 60 and ground lines 61 are relativelyreduced so that the area occupied by the bit cell 50 is reduced, asshown in FIG. 13B.

In an SRAM block in which the occurrence of a leakage current duringstandby is not allowed, on the other hand, the spacings between the bitlines BLn and /BLn and the ground lines 61 are relatively increased atthe expense of the area occupied by the bit cell 50, as shown in FIG.13C.

Instead of increasing the spacings between the bit lines BLn and /BLnand the ground lines 61, it is also possible to lay out power supplylines, not the ground lines 61, and provide the ground lines 61 inanother wiring layer different from the wiring layer 60 in FIG. 13C.

Although the eighth embodiment has described the SRAM block formed inthe semiconductor integrated circuit device, the present invention isnot limited to an SRAM block.

EMBODIMENT 9

A ninth embodiment of the present invention will be described hereinbelow with reference to the drawings.

In the ninth embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Layout of Different-Potential Nodes” and thecondition shown in FIG. 10 is assumed to be “Leakage Current”, which isthe first electric specification.

FIGS. 14A and 14B show an SRAM block formed in a semiconductorintegrated circuit device, of which FIG. 14A shows a circuit structureof the SRAM block in which power shutdown control is not performed andFIG. 14B shows a cross-sectional structure of bit cells and ground linesin the SRAM block. In FIGS. 14A and 14B, the description of the sameparts as shown in FIGS. 13A and 13B will be omitted by retaining thesame reference numerals.

Since the specification for the SRAM block according to the ninthembodiment is such that power shutdown control is not performed and datais retained during standby, it does not allow the occurrence of aleakage current during standby.

As shown in FIG. 14B, therefore, bit lines BLn and /BLn composing theSRAM block are formed in a first wiring layer 60A, while ground lines 61are formed in a second wiring layer 60B formed on the first wiring layer60A.

By thus separately providing lines at different potentials in thedifferent wiring layers 60A and 60B, a leakage current can surely besuppressed.

It is to be noted that a design rule value for the bit lines BLn and/BLn in the first wiring layer 60A may be the same as or different froma design rule value for the ground lines 61 in the second wiring layer60B. It is also possible to form the ground lines 61 in the first wiringlayer 60A and form the bit lines BLn and /BLn in the second wiring layer60B.

Although the ninth embodiment has described the SRAM block formed in thesemiconductor integrated circuit device, the present invention is notlimited to an SRAM block.

EMBODIMENT 10

A tenth embodiment of the present invention will be described hereinbelow with reference to the drawings.

In the tenth embodiment, the physical dimension to be applied shown inFIG. 1 is assumed to be “Bit-Cell Area” and the second electricspecification shown in FIG. 10 is assumed to be “Operating Speed andClock Frequency”. Designing methods which allow the determination of“Operating Speed and Clock Frequency” are delay control effected bypower supply voltage control, delay control effected by thresholdvoltage control, and RC delay control effected by using variations inthe number of wiring layers used in a layout.

By way of example, a description will be given to a structure whichperforms feedback control over a power supply voltage, a substratevoltage, or the like in a monitor circuit such that a clock frequencyserving as a basis for circuit operation and the frequency of themonitor circuit have a specified relationship therebetween, such as aphase locked loop (PLL).

The monitor circuit is a delay control circuit capable of controlling apower supply voltage or a substrate voltage. Even if the gate lengths oftransistors contained in an SRAM block become excessively short or longdue to micro-patterning variations and a signal delay time varies, anamount of delay in signal propagation time can be corrected by themonitor circuit.

In an SRAM block having such a monitor circuit, even if a leakagecurrent becomes more likely to flow as a result of reduced gate lengthswhen operational speed is to be increased by reducing the gate lengthsof the individual gates, as in the bit cell 50A contained in the SRAMblock shown in FIG. 11B, the provision of a leakage suppressing circuit54 can suppress an increase in leakage current during standby.

Thus, the tenth embodiment reduces the gate lengths of the individualtransistors in the SRAM block provided with the monitor circuit andthereby provides a logic cell having a small bit cell area and capableof performing high-speed operation, while suppressing variations inoperating speed.

On the other hand, the tenth embodiment increases the gate lengths ofindividual transistors in an SRAM block unprovided with a monitorcircuit, as in the bit cell 50B contained in the SRAM block shown inFIG. 12B, and thereby provides a logic cell having a large bit cell areaand small variations in operating speed.

Although the tenth embodiment has described the SRAM block formed in thesemiconductor integrated circuit device, the present invention is notlimited to an SRAM block.

EMBODIMENT 11

An eleventh embodiment of the present invention will be described hereinbelow with reference to the drawings.

The eleventh embodiment will refer to “Timing Values (a set-up value anda hold value for a clock signal) in the design patterns, which arecharacteristic of a third electric specification shown in FIG. 10.Designing methods which allow the determination of “Timing Values” areRC delay control effected by using variations in the number of wiringlayers used in a layout, selection of synchronous design/asynchronousdesign, the gate length of a delay circuit transistor for timingadjustment, and a layout which adjusts a distance from a clock driver.The set-up value is defined herein as a time interval between areference time determined by the clock signal and a time at which a datavalue should be determined prior to the reference time and the holdvalue is defined herein as a time during which the determined data valueis held.

(1) RC Delay Control Effected by Using Variations in Number of WiringLayers Used in Layout

Of the designing methods which satisfy the timing values of the electricspecification, RC delay control effected by using variations in thenumber of wiring layers used in a layout will be described first.

Each of SRAM blocks formed on one chip has a four-layer structureirrespective of the number of wiring layers of the entire chip (normallyfour to seven layers) such that the chip provides for any number oflayers.

If an SRAM block as shown in FIG. 11A is formed on a chip of which aspecification for the number of wiring layers is five to seventh layers,three wiring layers at the maximum are added to the original four layersto provide for a higher speed operation or a smaller area required ofthe SRAM block so that the SRAM block is designed as four to sevenwiring layers.

In an SRAM block of which a higher speed and a smaller area on the chipare required, multilayer wiring is used in a technically affordablerange so that a wire between other functional blocks in a wiring layeroverlying another wiring layer is not contained in the underlying layer.

Under such a condition that the gate lengths of individual gates in abit cell increase, the eleventh embodiment increases the gate lengthsand increases the number of wiring layers, thereby compensating for areduction in operating speed and an increase in bit cell area.

Under such a condition that the gate lengths of individual gates in abit cell do not increase, on the other hand, the eleventh embodimentreduces the gate lengths, thereby satisfying an operating speed requiredand also reducing the area occupied by the bit cell.

In this case, however, layout is performed such that the maximum numberof wiring layers in the SRAM block is four and a wire providing aconnection between other functional blocks is positioned above the SRAMblock.

The following is an answer to the question of whether the influence ofmicro-patterning variations on the timing values is increased ordecreased by variations in the number of wiring layers used in a layout.Since multilayer wiring containing a larger number of layers reduces atotal length of wiring and a wiring density, the absolute values ofresistance and capacitance can be reduced. Even if micro-patterningvariations occur at a given rate in a portion of each of the wiringlayers, therefore, the influence of the variations is negligible sincethe absolute value of the variation occurred is small.

If the flexibility of the multilayer wiring is high depending on therelationship between adjacent functional blocks, therefore, the absolutevalues of resistance and capacitance are reduced by using multilayerwiring containing a maximum permissible number of layers in designing achip. This reduces an absolute amounts of the timing values even if thefunctional block is disposed in a region of the chip wheremicro-patterning variations are relatively large.

If the flexibility of the multilayer wiring is low depending on therelationship between adjacent functional blocks, on the other hand, thefunctional block is disposed in a region of the chip wheremicro-patterning variations are relatively small.

This suppresses variations in timing allowance value when the variationsare considered in view of the flexibility of multilayer wiring on thechip and the magnitude of the micro-patterning variation.

(2) Selection of Synchronous/Asynchronous Design

Of the designing methods which satisfy the timing values of the electricspecification, the selection of synchronous/asynchronous design will bedescribed next.

In synchronous design, it presents a problem whether or not micromachingvariations impair the relationship between the set-up time, which is arelative timing difference between the clock signal and a data signal,an address signal, or the like, or the hold time and an allowance valuefor the set-up time or the hold time.

By contrast, asynchronous design basically receives no influence frommicro-patterning variations since a relative timing value, such as theset-up time or the hold time, does not exist.

In terms of limited design time and limited design resources, however,it is nearly impossible to design all functional blocks formed on thechip asynchronously. As a result, functional blocks designedsynchronously and functional blocks designed asynchronously exist inmixed relation on the chip.

If the functional blocks designed asynchronously are disposed in theregion of the chip where micro-patterning variations are small and thefunctional blocks designed synchronously are disposed in the region ofthe chip where micro-patterning variations are large, therefore,variations in timing allowance value when the variations are consideredcan be suppressed.

(3) Gate Width of Delay Circuit Transistor for Timing Adjustment

Of the designing methods which satisfy the timing values of the electricspecifications, the gate width of a delay circuit transistor will bedescribed next.

Because of large micro-patterning variations in the chip, in a delaycircuit which should inevitably be disposed in a region where variationsin gate width are large, the influence of the variations is reduced byincreasing the gate width even at the expense of a circuit area.

In the case where the delay circuit can be disposed in a region wherevariations in gate width are small, however, the gate width can bereduced by giving a higher priority to a reduction in circuit area.

(4) Layout for Adjusting Distance from Clock Driver

Of the designing methods which satisfy the timing values of the electricspecification, a layout for adjusting a distance from a clock driverwill be described next.

In general, a plurality of clock drivers are placed at positions on achip as close as possible to the regions to which a clock signal issupplied. Although the placement of a larger number of clock drivers isadvantageous to a design margin in timing design, the area is increasedthereby disadvantageously through the tradeoff between the number ofclock drivers placed and a circuit area.

If the magnitude of micro-patterning variation has dependence on thedistance from the center of the chip, the eleventh embodiment allows thedistance from each of the clock drivers to the corresponding one of theregions to which a clock is supplied to have a distribution dependent onthe distance from the center of the chip, thereby reducing variations intiming allowance value.

Although the eleventh embodiment has described the SRAM blocks formed inthe semiconductor integrated circuit device, the present invention isnot limited to SRAM blocks.

EMBODIMENT 12

A twelfth embodiment of the present invention will be described hereinbelow with reference to the drawings.

As shown in FIG. 15A, the twelfth embodiment assumes the physicaldimension to be applied shown in FIG. 1 to be “Bit Cell Area” and willrefer to “Memory Function”, which is a fourth electric specificationshown in FIG. 10. A designing method for determining “Memory Function”is the determination of whether or not a redundancy function isprovided.

FIG. 15B diagrammatically shows a plan structure of a chip-likesemiconductor integrated circuit device according to the twelfthembodiment and SRAM blocks formed on the chip.

As shown in FIG. 15B, a first SRAM block 17 having a capacity of 512kbits and a second SRAM block 18 having a capacity of 512 kbits areformed integrally on a principal surface of the chip 10 composed of,e.g., silicon.

The first SRAM block 17 has a redundancy function and contains bit cellseach occupying an area (S_bitcell) of 2.4 μm². On the other hand, thesecond SRAM block 18 does not have a redundancy function and containsbit cells each occupying an area of 3.5 μm².

Thus, the bit cells contained in the SRAM blocks according to thetwelfth embodiment have different areas depending on the presence orabsence of the redundancy function in the memory.

FIG. 16A shows a structure of the SRAM block having the redundancyfunction. FIG. 16B shows a structure of the SRAM not having theredundancy function. To impart the redundancy function to the SRAMblock, redundancy circuits including a redundancy row, a redundancymemory array, and a redundancy sense amp are added as shown in FIG. 16A.As for the area, it is simply increased with the addition of theredundancy circuits.

Even if micro-patterning variations in the fabrication process causesfaults in several bits, however, the redundancy function substantiallysaves the faulty bits by replacing the faulty bits with redundancy bits.Even if a defect density (DD value) is increased by reducing the sizesof the bit cells at a design stage and reducing a margin whenmicro-patterning variations are considered, the yield rate of an SRAMportion can be improved if consideration is given to the redundancyfunction. This achieves a reduction in effective DD value, whileachieving a reduction in the area occupied by each of the bit cells, asillustrated in FIG. 17.

As shown in FIG. 17, the yield rate is improved greatly in the casewhere the redundancy function is provided, which is indicated by thesolid curve A, and the effective DD value is reduced, compared with thecase where the redundancy function is not provided, which is indicatedby the broken curve B. By thus selectively using the SRAM blocksdepending on the presence or absence of the redundancy function and themagnitude of the bit cell area, the area occupied by the entire chip canbe reduced and the production yield can be improved.

If the effective DD value depends on the distance from the center of thechip, it is also possible to determine whether or not the redundancycircuits are provided depending on the distance from the center of thechip.

A description will be given herein below to the relationship between thearea occupied by each of the bit cells and the DD value.

(1) To reduce the area occupied by the bit cell, the design patternsizes of the individual parts, i.e., the gate, the source, the drain,and the like should inevitably be reduced so that the spacing betweenthe wires or the elements is also reduced. This increases thepossibility of a fault occurring under the influence of a minor defector pattern shift and increases the DD value.

(2) The area occupied by the bit cell varies with the number of contactsprovided in the bit cell (determination of the number of contacts) andthe DD value also varies with the number of contacts provided in the bitcell.

An example of the determination of the number of contacts will bedescribed with reference to FIGS. 18A and 18B.

FIG. 18A shows a plan structure of a first bit cell 70A provided withtwo contacts formed in a specified contact formation region. FIG. 18Bshows a plan structure of a second bit cell 70B provided with onecontact formed in a specified contact formation region. In FIGS. 18A and18B, the description of the same parts of the bit cells shown in FIG. 7will be omitted by retaining the same reference numerals.

As shown in FIG. 18A, if attention is focused only on the P-typetransistors of the first bit cell 70A, a P-type source contact 71provided on the common source of first and second P-type loadtransistors MP0 and MP1 is composed of first and second contacts 71 aand 71 b. Likewise, a first P-type drain contact 72 provided on thefirst P-type load transistor MP0 is composed of first and secondcontacts 72 a and 72 b, while a second P-type drain contact 73 providedon the second P-type load transistor MP1 is composed of first and secondcontacts 73 a and 73 b.

As shown in FIG. 18B, on the other hand, a P-type source contact 71provided on the common source of the first and second P-type loadtransistors MP0 and MP1 of the second bit cell 70B is composed of onecontact. Likewise, each of a first P-type drain contact 72 provided onthe first P-type load transistor MP0 and a second P-type drain contact73 provided on the second P-type load transistor MP1 is composed of onecontact. Such a relationship is also established in the same manner asin the first and second drive transistors MN0 and MN1 of the first andsecond bit cells 70A and 70B.

In the case where two contacts are provided on each of the source anddrain as in the first bit cell 70A, even if one of the two contactsbecomes faulty, the entire bit cell does not become faulty.

In the twelfth embodiment, the contact configuration described in (1) or(2) can be used selectively depending on the presence or absence of theredundancy function.

Although the twelfth embodiment has described the SRAM blocks formed inthe semiconductor integrated circuit device, the present invention isnot limited to SRAM blocks.

EMBODIMENT 13

A thirteenth embodiment of the present invention will be describedherein below with reference to the drawings.

A description will be given to “the case where required specificationsdiffer depending on the usage modes in the design patterns”, which is athird concept of the present invention.

Specifically, the description will be given to the case where aplurality of design rules are applied to each of the design rules shownin FIG. 1 according to the usage modes in the design patterns in thethirteenth and fourteenth embodiments.

First, usage modes in a semiconductor integrated circuit device will bedescribed.

If the future trend is toward the formation of a plurality of functionalblocks on one chip, it will be a rare case that all functional blocksare used only for one application. If a frame buffer is used as anexample, it will be used for various purposes as a frame buffer fordisplay, a frame memory for storing the result of an arithmeticoperation for compression or decompression, and the like, so thatrequirements placed on the frame memory differ.

If other functional blocks are to be designed or fabricated to satisfythe most stringent requirement which is placed with regard to conditionsfor design or fabrication, high costs should be paid. If a sufficientmargin is allowed for micro-patterning variations, as has been allowedconventionally, it becomes possible to uniformly fabricate all thefunctional blocks and design and test all the functional blocks inaccordance with the same specifications.

A description will be given to a method for changing the design rulesfor a chip in accordance with its various usage modes shown below undersituations forming the background of the present invention.

As shown in FIG. 19, the usage modes can be subdivided into the first toeighth usage modes.

In the first usage mode, a one bit fault is tolerated if a circuitelement is a memory element. In the second usage mode, data need not beretained during standby. In the third usage mode, it is sufficient tooperate for a relatively short period. In the fourth usage mode, anoperating speed may be relatively low (operation in a DC manner). In thefifth usage mode, repetitive pattern blocks having identical structuresare used. In the sixth usage mode, centroid (point-symmetric) layout isperformed. In the seventh usage mode, custom design (high-precisionphysical design) is performed. In the eighth usage mode, signaltransmission (small signal transmission, i.e., a wiring resistance maybe high) is performed by a differential operation.

As the thirteenth embodiment, a specific example of “One Bit Fault isTolerable” in the design patterns will be described.

As shown in FIG. 20A, the thirteenth embodiment assumes the physicaldimension to be applied shown in FIG. 1 to be “Bit Cell Area” and willrefer to “One Bit Fault is Tolerable” (except for Consecutive BitFaults), which is characteristic of the first usage mode shown in FIG.19.

FIG. 20B diagrammatically shows a plan structure of a chip-likesemiconductor integrated circuit device according to the thirteenthembodiment and SRAM blocks formed on the chip.

As shown in FIG. 20B, a first SRAM block 19 having a capacity of 512kbits and a second SRAM block 20 having a capacity of 128 kbits areformed integrally on a principal surface of a chip 10 composed of, e.g.,silicon.

The usage mode of the first SRAM block 19 is such that a one bit fault(point defect) is tolerated and the bit cell area (S_bitcell) therein is2.4 μm², which is relatively small. On the other hand, the usage mode ofthe second SRAM block 20 is such that a one bit fault (point defect) isnot tolerated and the bit cell area (S_bitcell) therein is 3.5 μm²,which is relatively large.

For example, in a frame buffer memory used merely for display, not as aframe buffer used for a digital arithmetic operation, 24 bits of colordata is required to display each pixel. To represent luminance data, 6bits are required. Even if a fault has occurred in one of the bits,however, it cannot be discriminated by human eyes.

Even if all the bits representing one pixel are faulty, one pixel in adisplay device having ten thousands of pixels arranged in 100 rows and100 columns accounts for only 0.01% of all the pixels, which is at alevel unrecognizable by human eyes and therefore tolerated. There islittle necessity to incorporate a redundancy function as described inthe twelfth embodiment into such a frame buffer memory. Even if it isincorporated, the redundancy function may be disposed appropriately in aregion where micro-patterning variations are large.

Specifically, a frame buffer for an application which requires a largernumber of pixels rather than a smaller number of point defects, such asthe first SRAM block 19 shown in FIG. 20B, needs a relatively largememory capacity so that a reduction in bit cell area is required. Inaddition, a redundancy function need not be incorporated therein since apoint defect is tolerated.

In an SRAM block in which a memory capacity need not be increased but adefect (error) is not tolerated because of its use for a digitalarithmetic operation, such as the second SRAM block 20, on the otherhand, the probability of a defect is reduced appropriately by relativelyincreasing the bit cell area.

Thus, according to the thirteenth embodiment, the first SRAM block 19which has a large capacity, exhibits a high degree of integration, andtolerates a point defect is disposed in a region of the chip 10 wheremicro-patterning variations are relatively large. By contrast, thesecond SRAM block 20 which has a smaller capacity than the first SRAMblock 19, exhibits a lower degree of integration than the first SRAMblock 19, and does not tolerate a point defect is disposed in a regionof the chip 10 where variations are relatively small. This reduces eachof areas occupied by the first and second SRAM blocks 19 and 20 andresultantly reduces the area of the chip 10.

Although the thirteenth embodiment has described the SRAM blocks formedin the semiconductor integrated circuit device, the present invention isnot limited to SRAM blocks.

EMBODIMENT 14

A fourteenth embodiment of the present invention will be describedherein below with reference to the drawings.

In the fourteenth embodiment, the physical dimension to be applied shownin FIG. 1 is assumed to be “Bit Cell Area” and the second usage modeshown in FIG. 19 is assumed to be “No Need to Retain Data duringStandby”

FIGS. 21A and 21B show an SRAM block formed in a semiconductorintegrated circuit device, of which FIG. 21A shows a circuit structureof the SRAM block in which power shutdown control is performed and FIG.21B shows a plan structure of bit cells contained in the SRAM block.

FIGS. 22A and 22B show an SRAM block formed in the semiconductorintegrated circuit device, of which FIG. 22A shows a circuit structureof the SRAM block in which power shutdown control is not performed andFIG. 22B shows a plan structure of bit cells contained in the SRAMblock.

It is to be noted that each of the bit cells 50A shown in FIG. 21A hasthe same structure as each of the bit cells 50 shown in FIG. 13A and thebit cell 50B shown in FIG. 21B has the same structure as the bit cell50A shown in FIG. 11B. In the drawings, like parts are designated bylike reference numerals.

Likewise, each of the bit cells 50B shown in FIG. 22A has the samestructure as each of the bit cells 50B shown in FIG. 14A and the bitcell SOB shown in FIG. 22B has the same structure as the bit cell 50Bshown in FIG. 12B. In the drawings, like parts are designated by likenumerals.

To use a semiconductor integrated circuit device having a memory circuitfor mobile applications, a leakage current in the memory circuit shouldbe suppressed during standby. Therefore, a method which most positivelysuppresses the leakage current is to turn OFF the power supply duringstandby.

However, since a memory circuit required to retain data also exists, ithas conventionally been impossible to turn OFF a power supply for a chipcontaining a memory circuit which retains data during standby. For amemory circuit formed on a chip, especially an SRAM circuit, a circuithaving a long gate length Lg and a large bit cell has been usedinevitably such that the problem of a leakage current does not occur.

If a power shutdown function performed by a switch 55 for power shutdownis incorporated in each of various SRAM circuits except for the SRAMcircuit which retains data during standby, as in the SRAM block shown inFIG. 21A, there is no probability of the occurrence of a leakagecurrent. Since bit cells 50A each having a small gate length Lg can beimplemented in the SRAM block having the power shutdown function, asshown in FIG. 22B, the bit cell area can be reduced.

Thus, according to the fourteenth embodiment, the SRAM block which neednot retain data and therefore contains the bit cells 50A each having arelatively small gate length Lg is disposed in a region of a chip wheremicro-patterning variations are large, as shown in FIG. 21A. On theother hand, the SRAM block which should retain data and thereforecontains the bit cells 50B each having a relatively large gate length Lgis disposed in a region of the chip where micro-patterning variationsare small, as shown in FIG. 22A. In either case, the area of the chipcan be reduced. This is because a power shutdown function need not beincorporated in the SRAM block containing the bit cells 50B.

In the SRAM circuit which should retain data during standby, as shown inFIG. 14A, wires (nodes) at different potentials are formed preferably indifferent wiring layers to reduce the probability of a short circuitoccurring between the wires at different potentials, as shown in FIG.14B.

Even if the SRAM block having a power shutdown function and the SRAMblock not having a power shutdown function are formed on one chip, thearea occupied by each of the bit cells 50A can be reduced.

Although the fourteenth embodiment has described the SRAM blocks formedin the semiconductor integrated circuit device, the present invention isnot limited to SRAM blocks.

1-16. (canceled)
 17. A semiconductor integrated circuit devicecomprising: a design pattern composed of a plurality of circuit elementsor the wires formed on a substrate, the design pattern having aplurality of minimum size values in a spacing between parts at differentpotentials during standby which differ depending on an electricspecification and a designing means for implementing the electricspecification.
 18. The semiconductor integrated circuit device of claim17, wherein the parts at different potentials during standby are formedin different layers.
 19. The semiconductor integrated circuit device ofclaim 17, wherein the electric specification is suppression of a leakagecurrent and the designing means includes at least one of power voltagecontrol, power shutdown control, threshold voltage control, andgate-to-source potential control.
 20. The semiconductor integratedcircuit device of claim 17, wherein the electric specification is anoperating speed and the designing means includes at least one of powervoltage control, threshold voltage control, and delay control effectedby using variations in the number of wiring layers used in a layout. 21.The semiconductor integrated circuit device of claim 17, wherein theelectric specification is a timing value and the designing meansincludes at least one of selection of synchronous design or asynchronousdesign, delay control effected by using variations in the number ofwiring layers used in a layout, a delay circuit for timing adjustment, agate size of a transistor, and a layout for adjusting a distance from aclock driver.
 22. The semiconductor integrated circuit device of claim17, wherein the circuit elements are memory elements and the designingmeans is a means for imparting a redundancy function for saving adefect. 23-41. (canceled)
 42. A method for designing a semiconductorintegrated circuit device, the method comprising the step of forming, ona substrate, a plurality of design patterns composed of circuit elementsor wires, wherein the plurality of design patterns include a spacingbetween parts at different potentials during standby and a plurality ofdesign rules are applied to the plurality of design patterns dependingon an electric specification of each of the design patterns and adesigning method for implementing the electric specification.
 43. Themethod of claim 42, wherein the parts at different potentials duringstandby are formed in different layers.
 44. The method of claim 42,wherein the electric specification is suppression of a leakage currentand the designing method includes at least one of power voltage control,power shutdown control, threshold voltage control, and gate-to-sourcepotential control.
 45. The method of claim 42, wherein the electricspecification is an operating speed and the designing method includes atleast one of power voltage control, threshold voltage control, and delaycontrol effected by using variations in the number of wiring layers usedin a layout.
 46. The method of claim 42, wherein the electricspecification is a timing value and the designing method includes atleast one of selection of synchronous design or asynchronous design,delay control effected by using variations in the number of wiringlayers used in a layout, a delay circuit for timing adjustment, a gatesize of a transistor, and a layout for adjusting a distance from a clockdriver.
 47. The method of claim 42, wherein the circuit elements arememory elements and the designing method is a method for imparting aredundancy function for saving a defect. 48-50. (canceled)